BPSC Tre 4.0 Computer Science MCQ | Half Adder_Digital Logic

BPSC Tre 4.0 Computer Science MCQ | Half Adder_Digital Logic.A Half Adder is a combinational digital circuit that adds two binary digits | tech blogs.

 Half Adder_Digital Logic MCQ

BPSC Tre 4.0 Computer Science MCQ | Half Adder_Digital Logic.A Half Adder is a combinational digital circuit that adds two binary digits and produces Sum and Carry outputs.


A Half Adder is a combinational digital circuit that adds two binary digits and produces Sum and Carry outputs.

1. A Half Adder is used to add:

A. Two decimal numbers
B. Two binary digits
C. Three binary digits
D. Two hexadecimal digits
Answer: B
Explanation: A Half Adder adds two 1-bit binary inputs.

2. Half Adder has:

A. Two inputs and one output
B. Two inputs and two outputs
C. Three inputs and one output
D. Three inputs and two outputs
Answer: B
Explanation:
Inputs: A, B
Outputs: Sum (S) and Carry (C)

3. Half Adder is a:

A. Sequential circuit
B. Memory device
C. Combinational circuit
D. Clocked circuit
Answer: C

4. Outputs of a Half Adder are:

A. Sum and Borrow
B. Difference and Carry
C. Sum and Carry
D. Carry and Overflow
Answer: C

5. Carry output of a Half Adder is generated when:

A. Any one input is 1
B. Both inputs are 0
C. Both inputs are 1
D. Inputs are different
Answer: C
Explanation: Carry = 1 only for A = 1 and B = 1.

6. Sum output of Half Adder is 1 when:

A. Both inputs are same
B. Both inputs are 1
C. Inputs are different
D. Both inputs are 0
Answer: C

7. For inputs A = 0, B = 1, the output of Half Adder is:

A. S = 0, C = 0
B. S = 1, C = 0
C. S = 0, C = 1
D. S = 1, C = 1
Answer: B

8. For inputs A = 1, B = 1, the output is:

A. S = 0, C = 0
B. S = 1, C = 0
C. S = 0, C = 1
D. S = 1, C = 1
Answer: C

9. Boolean expression for SUM in Half Adder is:

A. A + B
B. AB
C. A ⊕ B
D. (A + B)’
Answer: C

10. Boolean expression for CARRY in Half Adder is:

A. A + B
B. A ⊕ B
C. A’B + AB’
D. AB
Answer: D

11. Which logic gate is used to generate SUM?

A. AND
B. OR
C. XOR
D. NOR
Answer: C

12. Which logic gate is used to generate CARRY?

A. XOR
B. AND
C. OR
D. NAND
Answer: B

13. Half Adder can be implemented using:

A. AND and OR gates
B. XOR and AND gates
C. NAND gates only
D. NOR gates only
Answer: B
Explanation:

  • SUM = XOR
  • CARRY = AND

14. Half Adder cannot add:

A. Two bits
B. Binary numbers
C. Numbers with carry input
D. Single-bit numbers
Answer: C
Explanation: Half Adder has no carry input.

15. Half Adder differs from Full Adder because Half Adder:

A. Has carry input
B. Has three inputs
C. Has no carry input
D. Is a memory device
Answer: C

16. Half Adder is mainly used in:

A. Memory design
B. ALU design
C. CPU control unit
D. Sequential circuits
Answer: B

17. Which statement is TRUE?

A. Half Adder has carry input
B. Half Adder has two outputs
C. Half Adder is sequential
D. Half Adder uses clock
Answer: B

18. Half Adder can add multi-bit numbers directly.

A. True
B. False
Answer: B

19. Half Adder produces overflow.

A. True
B. False
Answer: B
Explanation: Overflow is related to signed multi-bit addition, not Half Adder.

20. Half Adder is a basic building block of:

A. Decoder
B. Encoder
C. Full Adder
D. Multiplexer
Answer: C

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