Computer Organization & Architecture (COA) | BPSC TRE Computer Science MCQ

 Computer Organization & Architecture (COA) MCQ

1. Who proposed the stored-program concept?
A. Charles Babbage
B. John von Neumann
C. Alan Turing
D. Dennis Ritchie

Answer: B (John von Neumann architecture is still the base of modern computers.)

2. Which unit performs arithmetic operations?
A. Control Unit
B. ALU
C. Memory
D. Register

Answer: B
ALU = Arithmetic Logic Unit performs arithmetic and logical operations.

3. The instruction cycle consists of:
A. Fetch only
B. Decode only
C. Fetch–Decode–Execute
D. Compile–Run

Answer: C

4. Which register holds the next instruction address?
A. MAR
B. PC
C. IR
D. ACC

Answer: B

5. Stored program concept means:
A. Data stored externally
B. Instructions stored in memory
C. Program stored in CPU
D. Separate instruction memory mandatory

Answer: B

6. Accumulator is used for:
A. Input storage
B. Intermediate arithmetic results
C. Address decoding
D. Cache control

Answer: B

7. MAR stands for:
A. Memory Address Register
B. Machine Address Register
C. Memory Access Region
D. Main Address Register

Answer: A
MAR → holds address
MDR → holds data

8. Control Unit generates:
A. Data signals
B. Control signals
C. Clock pulses only
D. Addresses only

Answer: B

9. Hardwired control is:
A. Flexible but slow
B. Fast but less flexible
C. Software controlled
D. Microprogrammed

Answer: B

10. Microprogrammed control uses:
A. Control memory
B. Cache
C. RAM only
D. Registers

Answer: A

11. Binary equivalent of (25)₁₀ is:
A. 11001
B. 10101
C. 11100
D. 10011

Answer: A

12. 1’s complement represents:
A. Positive numbers only
B. Signed numbers
C. Floating numbers
D. ASCII

Answer: B

13. Range of n-bit 2’s complement:

−2ⁿ⁻¹ to 2ⁿ⁻¹−1

14. Overflow occurs when:
A. Carry generated
B. Result exceeds range
C. Bit lost
D. Division occurs

Answer: B

15. ASCII uses:
A. 4 bits
B. 7 bits
C. 8 bits fixed originally
D. 16 bits

Answer: B
Extended ASCII = 8 bits.

16. Instruction format contains:
A. Opcode
B. Operand
C. Addressing mode
D. All

Answer: D

17. Zero-address instructions are used in:
A. Register machines
B. Stack machines
C. Memory machines
D. Pipeline systems

Answer: B

18. RISC architecture emphasizes:
A. Complex instructions
B. Few simple instructions
C. Microcoding
D. Large instruction size

Answer: B

19. CISC features:
A. Fixed instruction size
B. Simple instructions
C. Complex operations
D. Load/store only

Answer: C

20. Example of RISC processor:
A. x86
B. ARM
C. VAX
D. 8086

Answer: B

Addressing Modes :-

21. Operand inside instruction →  Immediate addressing

22. Address field contains memory location:- Direct addressing

23. Operand located using register value:- Register indirect addressing

24. PC-relative addressing used in:- Branch instructions

25. Auto-increment mode:- Register automatically updated after access.

26. Fastest memory:
A. Cache
B. Register
C. RAM
D. Disk

Answer: B

27. Cache memory reduces:
A. CPU speed
B. Access time
C. Memory size
D. Instruction count

Answer: B

28. SRAM is used in:- Cache memory

29. DRAM requires:- Refreshing

30. Virtual memory uses:
A. Paging
B. Segmentation
C. Both
Answer: C

31. Page fault occurs when:- Page not in main memory.

32. DMA stands for:- Direct Memory Access

33. DMA transfers data between:- I/O and Memory without CPU.

34. Interrupt driven I/O improves:- CPU utilization.

35. Polling is:- CPU repeatedly checks device status.

36. Priority interrupt decides:- Which device served first.

37. Pipelining improves:
A. Latency
B. Throughput

Answer: Throughput

38. Pipeline hazards:
A. Structural
B. Data
C. Control
D. All

Answer: D

39. Branch hazard caused by:- Conditional instructions.

40. Superscalar processors:- Execute multiple instructions simultaneously.

41. Ideal pipeline speedup = Number of stages.

42. Booth’s algorithm used for:- Signed multiplication

43. Restoring division restores:- Partial remainder.

44. Floating-point standard:- IEEE 754

45. Normalization ensures:- Leading digit non-zero.

46. Microoperation operates on:- Register data.

47. Control word specifies:- Microoperations.

48. Hardwired control is faster because:- No microinstruction fetch.

49. Microprogram stored in:-Control memory.

50. System bus contains:
A. Address bus
B. Data bus
C. Control bus
D. All

Answer: D

51. Address bus is:- Unidirectional.

52. Data bus is:- Bidirectional.

53. Bus arbitration resolves:- Bus conflicts.

54. Mapping types:- Direct, Associative, Set-associative

55. Fastest mapping:- Associative mapping.

56. Replacement policy example:- LRU.

57. Cache hit means:- Data found in cache.

58. Cache miss penalty:- Extra access time.

59. CPU performance depends on:
A. Clock rate
B. CPI
C. Instruction count
D. All

Answer: D

60. CPU Time = Instruction Count × CPI × Clock Cycle Time

61. MIPS measures:- Instruction execution rate.

Last Minute Notes:-
Stored Program Concept:-

• Proposed by John von Neumann
• Instructions + Data stored in same memory
• Single bus → Von Neumann bottleneck

Functional Units

• Input Unit
• Output Unit
• Memory Unit
• CPU → (ALU + Control Unit + Registers)

Instruction Cycle

Fetch → Decode → Execute → Store

Important Registers and their work

Register	Function
PC	Holds next instruction address
IR	Holds current instruction
MAR	Memory address
MDR	Memory data
ACC	Arithmetic Results

Overflow Rule:-

Overflow occurs if:

• Two positives → negative result
• Two negatives → positive result

Instruction Format

Opcode + Operand + Addressing Mode

Hierarchy Order (Fastest → Slowest) :-  Register → Cache → RAM → Disk → Tape

 Cache Memory

• Very fast
• Small
• Uses SRAM
• Reduces access time

Cache Terms

• Hit → Data found
• Miss → Data not found
• Hit Ratio = Hits / Total Access

Locality of Reference

• Temporal → Recently used
• Spatial → Nearby location

RAM Types

• SRAM → Fast, no refresh (Cache)
• DRAM → Needs refresh (Main memory)

Cache Mapping Techniques

Technique	Speed	Cost
Direct	Fast	low
Associative	Fastest	High
Set-Associatice	Balanced	Medium

Cache Terms

• Hit → Data found
• Miss → Data not found
• Hit Ratio = Hits / Total Access

DMA (Direct Memory Access) :- Transfers data without CPU. Faster for bulk transfer

Pipeline

Fetch → Decode → Execute → Memory → Write Back

Pipeline Improves:- Throughput (NOT latency)

Hazards :- 

• Structural
• Data
• Control (branch hazard)

Ideal Speedup :- Number of stages

Control Unit

Types:

1. Hardwired Control

• Fast
• Less flexible

2. Microprogrammed Control

• Flexible
• Slower
• Uses control memory

Bus Organization

System Bus =

• Address Bus (Unidirectional)
• Data Bus (Bidirectional)
• Control Bus

Bus arbitration → resolves conflict

Performance Formula

 CPU Time = Instruction Count × CPI × Clock Cycle Time

OR

Instruction Count × CPI / Clock Rate

Performance increases if:

• Clock rate increases
• CPI decreases
• Instruction count decreases

Tips

• 2’s complement → invert + add 1
• Cache uses → SRAM
• Main memory → DRAM
• PC holds → next instruction
• IR holds → current instruction
• Pipeline improves → throughput
• DMA → no CPU involvement
• Overflow → sign error

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